Page 30 - EngineerIT October 2021

ELECTRONICS

How to minimise the number and size of

output capacitors in power supply designs

By Frederik Dostal, field applications engineer

power supply’s output capacitors, (ESR) and equivalent series inductance (ESL). For one capacitor at the output of a
which are typically ceramic power supply, this formula is very easy to apply. For a more complex situation (see
A capacitors with values between Figure 1) with multiple capacitors in parallel and series inductances occurring due to the
100 nF and 100 μF, cost money, take layout (L layout), the calculation is not as easy.
up space, and, in the case of delivery In this case, a simulation tool such as LTspice is ideal. Figure 2 shows a circuit
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bottle necks, can be difficult to obtain. diagram that was quickly created for the situation in Figure 1. Different values, including
Thus, the question of how the number ESR and ESL, can be assigned to the individual capacitors. Assumed effects of the
and size of output capacitors can be board layout — for example, L layout — can also be considered. The voltage ripple is then
minimised arises time and time again. simulated at the output of the switching regulator and at the input of the load.
Output capacitors also affect the output voltage offset after load transients. This
Output capacitor effects effect can also be simulated with LTspice. Here, it should especially be noted that, within
Two effects of the output capacitors are certain limits, the control speed of the power supply control loop and the impedance of
critical here: the effect on the output the output capacitors are interrelated. A faster power supply control loop can decrease
voltage ripple and the effect on the the number of output capacitors needed to remain within a specific output control
output voltage after load transients. window following load transients.
First, a general remark should Last but not least, the LTC3311-1 has adaptive voltage positioning (AVP). AVP can
be made about the term ‘’output utilise the entry error voltage budget and reduce the number of output capacitors, on top
capacitor’’. These capacitors can be of a reduction the designer may achieve, by increasing the loop bandwidth.
found on the output of a power supply. AVP raises the output voltage slightly in a low load condition and decreases the
However, many electrical loads (power output voltage slightly during a high load condition. Then, if load transients occur, more of
consumers), such as FPGAs, require the dynamic output voltage deviation is within the allowed output voltage range.
a certain number of input capacitors. Using LTpowerCAD from Analog Devices is recommended for finding out which control
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Figure 1 shows a typical design of a loop optimisations can be made and how many of the output capacitors can be eliminated.
power supply with a load, an FPGA.
If the physical distance between the
voltage generation and the consumer on
the circuit board is very small, the clear
distinction between the output capacitor
of the power supply and the input
capacitor of the load becomes blurred.
A differentiation is usually achieved
through a certain physical separation,
which results in a significant parasitic Figure 1: An LTC3311 switching regulator with the corresponding output capacitors and input
inductance (L layout). capacitors of a connected FPGA.
The formation of capacitors at the
output of a power supply determines
the voltage ripple in a step-down (buck)
switching regulator. The rule of thumb
stating that the output ripple voltage
corresponds to the inductor ripple
current, times the impedance of the
output capacitors, applies here:

This impedance, Z Cout, is made up of
the size and number of capacitors as Figure 2: Using LTspice for evaluating different capacitors at the output of a power supply in
well as the equivalent series resistance a system.

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