Page 29 - EngineerIT November 2021
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AUTOMATION AND CONTROL



           As described in Example 1, the AD7768-1’s digital filter   EXAMPLE 3
        also has no rejection at the frequency band around the ADC’s   An alternative approach to an IEPE sensor interfacing DAQ signal chain
        sampling frequency. In full power mode, the ADC’s effective   design is described in CN0540.
        sampling frequency is at 16.384 MHz. An active anti-aliasing filter   The CN0540 design supports a unipolar input range of 0 V to 24 V.
        is constructed with the ADA4945-1 to help the digital filter achieve   It is suitable for a non-channel isolated DAQ system interfacing with
        adequate overall out-of-band signal rejection across frequency. The   IEPE sensors without case isolation, in which case both the IEPE sensor
        design is a third-order low-pass filter with multi-feedback architecture   and the DAQ signal chain share a common earth ground. This design
        and a near Butterworth response. Another low-pass pole is added   supports DC coupling to an IEPE sensor. Even though piezo sensors do
        by an RC circuit in front of the ADA4610-1 buffer amplifier to help   not support responses down to DC, DC coupling gives this signal chain
        further increase the aliasing rejection at FS. The overall signal chain   the advantage of extracting low frequency vibrations without the start-
        frequency response has a –three dB corner at 440 kHz to minimise   up delay from a low bandwidth AC-coupling circuit.
        the magnitude and phase distortion to the in-band response. The   In comparison, the signal chain design shown in Example 2
        magnitude droop caused by the AAF at 100 kHz is less than ten mdB.   supports a bipolar input signal. It needs to operate in AC-coupled mode
        The magnitude response at                              in order to interface with an IEPE sensor, but this ±12.4 V input range
        16.3 MHz is around –108 dB. This, combined with the brick wall   and the high input impedance make it more suitable for multipurpose
        digital filter of the AD7768-1, produces an alias free signal chain that   DAQ systems.
        is capable of rejecting all out-of-band signals by at least 105 dB.
                                                               Summary
        Isolation and power management                         In conclusion, this article has detailed how the choice of system
        The digital and power isolation and power management solution will   architecture, sensor type and analysis methods can dramatically
        not be discussed in detail here. Solutions such as the ADP1031 can   impact the DAQ signal chain design in a condition monitoring system.
        provide SPI interface plus ±15 V and 5 V supply voltage across isolation.   The design considerations discussed here, along with the example
        An ADuM140D high speed digital isolator can be used to provide   reference designs, will hopefully help system designers make the best
        MCLK and SYNC_IN signals across isolation for across channel sample   design choices for their condition monitoring systems.   n
        synchronisation.
                                                               To learn more about Analog Devices’ condition-based monitoring
         Table 2. Example 2 DAQ Characteristics                system-level solutions, visit analog.com/CbM. In South Africa the
         Max input range ±12.4 V pseudo differential           contact person is Conrad Coetzee at ccoetzee@arrow.altech.co.za.
         Max flat bandwidth (–3 dB) 110 kHz
         Sinc5 filter ODR max 1024 kSPS (–3 dB BW = 209 kHz)    About the author
                                                                Naiqian Ren is an applications engineer with
         Dynamic range over 110 kHz BW Better than 105 dB
                                                                the Precision Converter Technology Group at
         THD at 1 kHz near full-scale input Better than –105 dB  Analog Devices in Limerick, Ireland. Naiqian
         Gain error drift* 10 ppm/°C                            joined ADI in 2007 and has a bachelor’s
         Offset error drift* 5 μV/°C                            degree in electrical engineering from the
         Power consumption with sinc5 filter 110 mW             Dublin City University and a master’s degree
                                                                in VLSI systems from the University of
         Power consumption with brick wall filter 130 mW
                                                                Limerick. He can be reached at naiqian.ren@analog.com.
         *Not including error from resistor matching


















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