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RADIO COMMUNICATION



        the same PLL (either one or two) and the same hop tables and TDD   this restriction can be removed.
        timing configurations. The MCS capability provided by the ADRV9002   ADRV9002 tracking calibrations are usually not performed during
        could be enabled to ensure that multiple channels on the same   fast FH. However, the initial calibrations are performed based on
        or different ADRV9002 devices are fully synchronised with each   multiple frequency regions according to users’ FH configurations to
        other with deterministic latency. Phase synchronisation can also be   achieve the best possible performance.
        achieved through MCS, which is performed each time PLL retunes
        frequency. With MCS, multiple channels could achieve synchronicity   FH performance evaluation using ADRV9002 transceiver
        even during FH, making the ADRV9002 an attractive solution for   evaluation software (TES)
        MIMO diversity applications involving FH. More detailed descriptions   FH performance can be evaluated thoroughly through the ADRV9002
        regarding the requirements and limitations of using MCS during FH   TES with the evaluation board. Both the Xilinx® ZC706 and ZCU102
        can be found in the ADRV9001 System Development User Guide. 2  FPGA boards are supported by TES.(2) As shown in Figure 11, the
           For channel multiplexing, each pair of channels uses one PLL and   FH configuration pages are easy to use to configure FH parameters,
        performs FH independently from each other. One limitation is that the very   including FH operation mode, the hopping tables, the GPIO setting, the
        fast FH, which requires two PLLs for a pair of transmit and receive channels,   TDD timing, etc. FPGA synchronisation features are built into the TES
        can’t be applied for channel multiplexing with one ADRV9002 device.  to allow users to accurately control the TDD timing so that the transmit
           Besides 2T2R mode, it is worth mentioning that the ADRV9002   or receive frames can be fully synchronised with hop frames. Many FH
        also supports 1T2R and 2T1R operations for FH, which provides   examples are also provided in TES for users to further explore.
        greater flexibility to meet users’ specific requirements.
                                                               Conclusion
        Support of FH with DPD operation                       FH is one of the advanced system features provided by the next-
        The ADRV9002 also supports DPD operation for both narrow-band and   generation SDR transceiver, the ADRV9002. With two PLLs, multiple
        wide-band applications. It corrects the non-linearity of the power amplifier   FH modes, and flexibility in loading and indexing hop tables, the
        (PA) to significantly improve PA efficiency while achieving standard   ADRV9002 empowers users with great FH capabilities to handle various
        compliant adjacent channel power leakage ratio (ACPR) performance.  applications and achieve advanced system requirements. All features
           One advanced feature of the ADRV9002 is that DPD can be   can be thoroughly evaluated through the ADRV9002 TES and Software
        performed together with FH. In such a case, the ADRV9002 allows   Development Kit (SDK).                n
        users to configure up to eight frequency regions, and the DPD
        algorithm creates an optimal solution for each frequency region. A   For more information on Analog Devices contact Conrad Coetzee at
        DPD solution as a set of coefficients can also be stored and loaded at   ccoetzee@arrow.altech.co.za
        the end and the beginning of a transmission, respectively, for each
        region. This ensures PA linearity for the entire hop frequency range.  References
           Since DPD is an adaptive filtering process that must capture a   1.  John G. Proakis. Digital Communications, 3rd edition. McGraw-Hill, March 1994.
        set of samples periodically for coefficient computation, the hopping   2.  UG-1828: ADRV9001 System Development User Guide. Analog Devices, Inc.,
                                                                 December 2020.
        frame length needs to be sufficiently long to satisfy the DPD capture   3.  Kao Chin-Han. “Performance Analysis of a JTIDS/Link-16-Type Waveform
        length requirement. However, in cases when users only utilise the   Transmitted over Slow, Flat Nakagami Fading Channels in the Presence of
        initially loaded DPD coefficients without the need for DPD updates,   Narrowband Interference.” Naval Postgraduate School, 2008.

                                                                                          About the Author
                                                                                          Mizhou (Michelle) Tan is a product
                                                                                          applications engineer with Analog
                                                                                          Devices. She has supported
                                                                                          the design and development
                                                                                          of RF transceiver products and
                                                                                          applications for about three years.
                                                                                          Prior to joining ADI, she received her
                                                                                          B.S. and M.S degrees in electrical
                                                                                          engineering from Sichuan University
                                                                                          in China and her Ph.D. degree in
                                                                                          electrical and computer engineering
                                                                                          from New Jersey Institute of
                                                                                          Technology in 2004. After that, she
                                                                                          worked as an algorithm, system and
                                                                                          software engineer in Agere Systems,
                                                                                          LSI Logic, and Intel Corp. from
                                                                                          2004 to 2018. She has published
                                                                                          more than 15 papers in technical
                                                                                          conferences and journals and owns
                                                                                          nine issued patents in wireless
                                                                                          communication and digital signal
                                                                                          processing area. She can be reached
                                                                                          at mizhou.tan@analog.com.
        Figure 11: Configure FH through TES.



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