Page 18 - Issue 2 2023

ELECTRONICS

the other at 3.0 V to 14.0 V. The digital input logic voltage is
independent of the supply voltages on these parts. The input
logic can be anywhere from 1.2 V to 5.5 V, which eliminates
any need for logic level shifters.
Jitter tolerance and clock generation
Digital input Class D audio amplifiers usually present a new
challenge for clock jitter. For good audio quality, most digital
input amplifiers require fairly low levels of jitter on BCLK or
MCLK. The jitter tolerance is often not quoted in the data
sheet; when jitter tolerance is quoted, the typical specification
is ~200 ps of rms jitter. High levels of clock jitter will typically
degrade either the amplifier’s dynamic range or the full scale
THD + N performance. Figure 4: Fractional-N PLL vs. cycle-skipped clock implementations.
In many systems, the reference oscillator for the
application processor is not a convenient multiple of the BCLK,
so providing a low jitter clock for the amplifier is not easy.
For example, 13 MHz is a common crystal frequency used for
GSM phones and 27 MHz is commonly used in video solutions.
Neither of these reference frequencies is a convenient multiple
of the 44.1 kSPS or 48 kSPS audio sample rates. These systems
will, therefore, often implement a complicated fractional-N PLL
to create the clock for the audio. In some cases, the solution
will require a separate audio reference oscillator, which
increases complexity and bill of materials (BOM).
An alternative and preferable solution is a digital input
amplifier that can tolerate high clock jitter without degrading
the audio performance. Such an amplifier will reduce system
complexity. In the simplest case, a cycle-skipping clock can be
used to generate BCLK, but this generates extraordinarily high Figure 5: Dynamic range degradation with 11.5 ns rms cycle-skipped
clock jitter.
jitter. If a 13 MHz reference clock is cycle-skipped to create a
6.144 MHz BCLK (48 kSPS × 128 OSR), then the peak jitter will
be 38.4 ns and the rms jitter will be 22.2 ns (Figure 3). This Conclusion
represents two orders of magnitude higher jitter than most Digital input filterless Class D audio amplifiers allow simple
DACs can tolerate. board level implementation with no I C, no MCLK, no level
2
These new Class D audio amps, however, still produce shifting and no EMI filtering. They provide high efficiency, low
>103 dB dynamic range performance with this amount of EMI, and high output power. The MAX98357 and MAX98360
clock jitter. A cycle-skipped clock can be created with a small are available in a WLP or QFN package and can produce 3.2 W
number of digital gates on the application processor. The new of output power. The MAX98365 is available in a WLP package
devices do not need the oscillator or a loop filter that would and can produce 17.6 W of output power.
otherwise be required in a PLL solution. See Figure 4.
Reference
Jitter tolerance test results 1. Matt Felder, Patrick Gallagher and Brian Donoghue. “Analyzing Audio
Test results show that the MAX98357, MAX98360, and DAC Jitter Sensitivity.” EDN Network, September, 2012.
MAX98365 dynamic range does not degrade with the cycle-
skipped jittered clock. These parts outperform the 120 dB DAC About the author
by more than 20 dB with the jittered clock. Further details Matt Felder joined Analog Devices in 2009 as an analog design
on jitter tolerance in sigma-delta DACs can be found in a engineer. His work includes audio DACs, audio ADCs, multi-
companion article. 1 channel SAR ADCs, audio amps, a video DAC, an FM radio
receiver, and a multi-format battery charger. Matt is a senior
member of the IEEE and has 47 issued patents. He has a B.S.E.E.
from Texas A&M and an M.S.E.E. from UT Austin.

Analog Devices is represented in South Africa by Altron Arrow.
For more information email Conrad Coetzee at
Figure 3: A 12.288 MHz MCLK from a cycle-skipped 25 MHz clock. ccoetzee@arrow.altech.co.za

18 | EngineerIT Issue 2 | 2023 SUBSCRIBE FREE