Page 17 - EngineerIT April 2022

Table 2: Channel-Level Power Saving Modes and the Required Wake-Up Time
Channel Components Powered Down Mode 0 Mode 1 Mode 2
highest power consumption around 1800
mW with all the highest power consumption Analog and Digital Data Path X X X
options enabled.
Based on Table 1, if an application has Transmit Tx Internal PLLs X X
a relaxed performance requirement, by Tx PLL LDOs and Channel LDOs X
selecting the lowest power consumption
option for each component, a total power Analog and Digital Data Path X X X
saving of about 480 mW could possibly
be achieved with this profile. Note: the Receive Rx Internal PLLs X X
component-level power saving options Rx PLL LDOs and Channel LDOs X
are mainly static, which means once
configured during the device initialisation Wake-Up Time at Different Configurations Mode 0 Mode 1 Mode 2
stage, they could not be changed
dynamically on-the-fly. One exception is Approximate RF PLL REF CLK = 30 MHz 4.5 350 500
Power-Up Time (μs)
the selection between the HP ADC or the with RF PLL Normal RF PLL REF CLK = 50 MHz 180 380
LP ADC, which allows changing on-the-fly Calibration Mode
through an API command. and Different RF RF PLL REF CLK = 100 MHz 170 370
Another static power saving option PLL REF CLK Rates
worth mentioning, is related to the Approximate RF PLL REF CLK = 30 MHz 100 300
configuration of one of its power domains. Power-Up Time (μs)
The ADRV9001 requires five different with RF PLL Fast RF PLL REF CLK = 50 MHz 60 260
power supply domains: 1 V digital Calibration Mode
(VDD_1P0), 1.8 V digital (VDD_1P8), and Different RF RF PLL REF CLK = 100 MHz 40 240
1 V analogue (VDDA_1P0), 1.3 V PLL REF CLK Rates
analogue (VDDA_1P3), and 1.8 V analog
(VDDA_1P8). Among them, the VDDA_1P0, time to wake up to resume the normal operation.
which is used to power all the transmit One method to power up and down channels is to use the channel enable signal (TX_
and receive channel LO circuits, is optional. ENBALE/RX_ENABLE) rising and falling edge, respectively. As shown in figure 5, the channel
This domain can be powered using internal being powered down starts to wake up at the corresponding enable signal rising edge and it
low dropout (LDO) regulators, which takes some time to become fully operational. If more channel components are powered down,
generate the 1 V required. Alternatively, then more wake-up time is required. The user should evaluate if the required wake-up time can
it can be powered externally by bypassing satisfy the transmit and receive channel transition timing requirement in their TDD applications.
some of the ADRV9001 internal LDO Three different modes of channel-level power saving are provided: Mode 0, Mode 1,
regulators, which is desirable to achieve and Mode 2. Each higher mode powers down additional channel-associated components
more power saving by turning off the LDO by requiring a longer wake-up time. Table 2 summarizes these three modes along with
regulators and applying a higher efficiency the required approximate wake-up time at different RF PLL calibration modes and RF PLL
external power source. Note: all the reference clock rates.
3
measurements performed in this article As shown in table 2, a higher channel-level power saving mode powers down additional
use internal LDO regulators to power up channel components at the expense of longer wake-up time. By default, the channel power
the VDDA_1P0 power domain. saving Mode 0 is always enabled if the user does not configure other modes. It powers down
analog and digital datapath components such as mixers, converters, filters, etc. when the
Channel-level power saving channel is idle. In Mode 0, only the RX_ENABLE and TX_ENABLE signals can be employed to
Different from the static component-
level power saving, channel-level power
saving is dynamic. It is designed for
TDD operations specifically. As shown
in figure 5, in TDD, transmit and receive
operations are time multiplexing with
each other. While one channel is active,
the other channel is idle; therefore, it
could be powered down to reduce power
consumption. Different from component-
level power saving, it does not result in
any performance penalty by powering
down the idle channel, but it takes more Figure 5: Channel-level power saving in a general TDD operation.

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